Discussion

LCD max resolution & refresh

7 2932
Can I get 1920x1080p60 out of LCD connector? I'd like to feed a 19" panel without using HDMI conversion.

My understanding is that a panel can run LVDS or RGB mode.

How does dual channel LVDS apply here?

I expect I'd be modifying LCD in fex but could not understand how SSD2828 applies:
fex guide

Thanks, dB
Support LVDS interface with single/dual link, up to 1920x1080@60fps
Support RGB interface with DE/SYNC mode, up to 2048x1536@60fps
Support serial RGB/dummy RGB/CCIR656 interface, up to 1280x720@60fps

About dual monitor: http://forum.lemaker.org/thread- ... inch_lvds_lcd_.html

For 1920x1080p60 I'd need dual channel LVDS.

I see from A20 datasheet p. 243 that the LVDS1 signals would be brought out on portD10 -D19 ( using mux 1 ) and that these connect to CON2 on the Pro ( e.g. pin 29 etc ). I saw single channel LVDS done in this thread:
[url=http://forum.lemaker.org/forum.php?mod=viewthread&tid=10877&highlight=lvdshttp://forum.lemaker.org/forum.p ... &highlight=lvds]here[/url]

But what would control single versus dual channel LVDS? Would my selections in a fex file of LCD and 1920x1080p60 cause dual channel?

A20 manual

I see in the fex config there is a variable for single vs dual - OK here goes...

Trying first to get a 1024 x 768 panel hooked up on Pro. Seeing weird stuff on LVDS D2 pos & neg ( LCD_D4, LCD_D5 - pins 17 and 19 on CON2 ).

Specifically I see a 65MHz clock superimposed over a signal that shows 5 microsecond low pulses every 21 us ( a line ).  

I have a black fullscreen test pattern which I can see fine when I use a HDMI script.bin. Running that pattern over LVDS has LVDS D0 & D1 seem to be valid LVDS - both are 1.24 V for pos and 1.43V for the neg.

I get backlight from another board - I used two FFC breakout boards from here: fpc board

Anybody have suggestions? Attached is my fex file. My panel expects clock info only on the CLK+ and CLK- , no separate HSYNC VSYNC or DE.

BananaProLCD.tar

30 KB, Downloads: 6

fex file

PS on CLK I see reasonable 65MHz - some noise but using scope math the common mode noise cancels out. FWIW I see the voltages on D0 switch when going from BLK to a RED test pattern.

PPS - I'll have to admit I'm not completely clear on how the sync works at the panel - I suspect timing is generated from having the differential data signals be neither hi nor low as I can decipher from the datasheet. If so can the Pro support this type of signalling? ( How? )

Final_Specification_TM080TDH01_V1.0.pdf

718.41 KB, Downloads: 15

my panel

Sorry for the continued blabbing...So the panel seems to require D2 bits 6,5,4 having DE, VSYNC, and HSYNC respectively based on the SN75LVDS83b that feeds in in a working system. Still cant explain the superimposed clock. More tomorrow.

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